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Design Verification Fundamentals
Why verification is a separate discipline from design, how a testbench evolves from directed tests to constrained-random with coverage, and how assertions pin down protocol behaviour.
3 modules ~21 min totalSystemVerilogVCSVerilator
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Curriculum Syllabus
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1
What Verification Is Actually For
Design asks 'does this implement the spec'; verification asks 'have we shown it does across everything the spec permits'. The second question is the harder one.
2
Testbench Architecture: Driver, Monitor, Scoreboard
The standard decomposition of a testbench into pieces that generate, observe and compare, and why separating them makes tests reusable.
3
Coverage and Assertions: Measuring and Pinning Behaviour
How coverage tells you what you have actually exercised, and how assertions check relationships across time instead of single instants.