Static Timing Analysis
How a timing tool proves a design meets its clock period without simulating: paths, slack, the setup/hold pair, clock modelling, and variation across corners.
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Curriculum Syllabus
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Timing Paths and Slack
What the tool actually analyses — four path types — and how a single number, slack, decides pass or fail.
Clock Modelling: Latency, Skew, Jitter, Uncertainty
The clock is not a perfect abstraction — real clocks have delay, mismatch and noise, and each enters the timing equations differently.
Variation, Corners, and OCV
No two transistors are identical and no chip runs at one condition — how analysis across process, voltage and temperature keeps a design working in the field.
Closing Timing: Reading a Report and Choosing a Fix
Turning a negative-slack report into a diagnosis, and matching the fix — sizing, buffering, restructuring, retiming — to the actual cause.