RTL Design with Verilog
What a hardware description language is really describing, the subset that synthesises cleanly, and the timing habits that keep your design correct once it runs at speed.
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Curriculum Syllabus
All modules are open and public. Jump directly into what you need or follow in sequence.
What a Verilog Module Actually Describes
Verilog does not describe a sequence of steps — it describes hardware that exists simultaneously. Building that mental model first prevents most beginner confusion.
Combinational Logic Without Latches
Writing if/case logic that always produces a value, and understanding why 'incomplete assignment' is the most common structural bug in RTL.
Registers, Edges, and Blocking vs Non-blocking
How to write a proper clocked register, why the choice of assignment operator is a correctness decision, and the one rule that prevents race bugs.
Driving a Design With a Self-checking Testbench
Separating design from stimulus, checking results automatically rather than eyeballing waveforms, and the difference between directed and random tests.